1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device.
2. Description of the Related Art
As conventional nonvolatile semiconductor memory, NOR flash memory and NAND flash memory have been widely used. In recent years, there has been proposed a flash memory (hereafter referred to as “2Tr flash memory”) combining the advantages of both NOR flash memory and NAND flash memory. A memory cell in a 2Tr flash memory comprises two MOS transistors. One of the MOS transistors, serving as a nonvolatile memory section, comprises a stacked structure of a control gate and a floating gate and has its drain electrode connected to a bit line. The other MOS transistor has its source electrode connected to a source line and is used for selection of the memory cell.
The write operation in the 2Tr flash memory is described below. During write, a write voltage fed from a write circuit is applied to the drain electrode of the MOS transistor that serves as a memory section. The write voltage causes the charge to become a hot carrier and to be transferred to the floating gate of the “memory” MOS transistor. The state in which the threshold voltage of the memory cell is raised due to accumulation of the charge on the floating gate is the “0” data state. The “1” or “0” of the data is decided by the presence or absence of the charge in the floating gate.
The write circuit includes latch circuits, each latch circuit being formed of two inverters, each inverter being configured by an nMOS transistor and a pMOS transistor. The inverter has a positive side power supply terminal and a negative side power supply terminal. If the voltage applied to the positive side power supply terminal and that applied to the negative side power supply terminal become equal, the data latched in the inverters is destroyed.
As a method of solving this problem, Japanese Unexamined Patent Application Publication No. 2005-317138 proposes a method of controlling the applied voltage immediately before the write operation so that at first the voltage applied to the negative side power supply terminal is lowered, and then the voltage applied to the positive side power supply terminal is lowered. However, in this method, the voltage applied between the positive and negative side power supply terminals becomes large at the point of time when the voltage applied to the negative side power supply terminal is first lowered.
Furthermore, the negative voltage applied to the negative side power supply terminal of the inverter is supplied also to the substrate part of all memory cells. Consequently, there has been a problem that the above-described large voltage may be applied between the drain electrodes and substrate part of non-selected memory cells, giving rise to a weak write state and resulting in a faulty write operation.